Thermal and Power management of Embedded High-Performance Computing

Andrea Bartolini and Luca Benini

Presentation title

Thermal and Power management of Embedded High-Performance Computing


Andrea Bartolini and Luca Benini


University of Bologna

Presentation type

Presentation of a research group from one or more scientific institutions


The end of Dennard’s scaling theory, for which at every technology generation the processor performance increases at the same power cost, has opened to parallelization as a means for increasing average throughput, keeping the power consumption limited [Borkar 1999]. By embedding multiple cores on the same silicon die, the performance “race,” led by the Moore’s Law, moved to integrate an ever-growing number of cores on the same chip area. In submicron technologies, the supply voltage no longer scales with feature size, leading to a power density increase that results in high and unbalanced temperatures. Common cooling infrastructures fail in counteracting it as they are constrained by cost (e.g., data centers consume the 50% of the energy to power cooling systems [Pow 2007]) and form factor (e.g., in mobile phones active cooling is infeasible [Luo 2008]). In this power-limited computing scenario the parallelism has shown its benefits on performance [Asanovic et al. 2006], but in upcoming and future technology generations all the units on a die cannot remain simultaneously active for a long period, as their total power consumption would exceed the maximum Thermal Design Power (TDP), leading to a thermal runaway.

When it comes to hardware mechanisms to protect the die from over temperature (referred as thermal management) today’s processors use two mechanisms: (i) dynamic voltage and frequency scaling (DVFS - ACPI P-states) as well as (ii) duty-cycling (Throttling - ACPI T-states). Thanks to turbo logic, cores can run at frequencies above the nominal TDP frequency without incurring in overheating and voltage drop problems. Duty-cycling is used as protection mechanism when die temperature exceed a critical threshold. However thermal throttling is strongly detrimental to core performance as the performance loss increases linearly with the power reduction. Differently for DVFS low-power states instead the performance loss scales sub linearly with the power reduction.

Clearly when embedded systems, with their limited power budget as well as their form factor, meet high performance requirements thermal design become a critical issue as active cooling strategies becomes less feasible and temperature as well as power management need to protect from thermal runaway as well as limit the performance reduction. Handling DVFS states to fulfil these requirements require to predict temperature evolutions, maximize the performance of application. Clearly this need to be tailored to the specific managed device, environmental conditions and workload characteristics.

In this presentation, we will discuss novel approaches to self-learn power and temperature models directly from the target device and combine this knowledge with optimal control loops to guarantee safe working temperature as the same time of maximum performance.

[Borkar 1999] S. Borkar. 1999. Design challenges of technology scaling. IEEE Micro 19, 4 (1999), 23–29.
[Pow 2007] Active Power, Inc. 2007. Data center thermal runaway. A review of cooling challenges in high density mission critical environments. White Paper. (2007).
[Luo 2008] Z. Luo, H. Cho, X. Luo, and K.-i. Cho. 2008. System thermal analysis for mobile phone. Appl. Therm. Eng. 28, 14–15 (2008), 1889–1895.
[Asanovic 2006] K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S.W.Williams, and K. A. YelickAsanovic. 2006. The Landscape of Parallel Computing Research: A View from Berkeley. Technical Report. UC Berkeley.

Additional material

  • Presentation slides: [pdf]