## Presentation title

On minimising the maximum expected verification time## Authors

Toni Mancini, Federico Mari, Annalisa Massini, Igor Melatti, Ivano Salvo and Enrico Tronci## Institution(s)

Model Checking Lab, Sapienza University of Rome## Presentation type

Technical presentation## Abstract

Cyber Physical Systems (CPSs) consist of hardware and software components. To verify that the whole (i.e., software + hardware) system meets the given specifications, exhaustive simulation-based approaches (Hardware In the Loop Simulation, HILS) can be effectively used by first generating all relevant simulation scenarios (i.e., sequences of disturbances ) and then actually simulating all of them (verification phase). When considering the whole verification activity, we see that the above mentioned verification phase is repeated until no error is found. Accordingly, in order to minimise the time taken by the whole verification activity, in each verification phase we should, ideally, start by simulating scenarios witnessing errors (counterexamples). Of course, to know beforehand the set of such scenarios is not feasible. In this paper we show how to select scenarios so as to minimise the Worst Case Expected Verification Time.

## Additional material

- Presentation slides: [pdf]
- Full paper:
Toni Mancini, Federico Mari, Annalisa Massini, Igor Melatti, Ivano Salvo, Enrico Tronci.

*On minimising the maximum expected verification time*.

Information Processing Letters, 122, pages 8-16, 2017.

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