Using MDA to support software-firmware co-design and co-verification on Virtual Platforms

David Perillo

Presentation title

Using MDA to support software-firmware co-design and co-verification on Virtual Platforms


David Perillo


Elettronica SpA

Presentation type

Technical presentation


The industrial approach to the design, realization, technical management, operations, and retirement of a system, is technically referred to as System Engineering (SE). The standard approach to SE relies on documents written in natural language as the primary source of information. In the domain of hardware-software (embedded) systems, the SE activity is in charge to evaluate the correctness and quality of the deployed product is referred to as “Integration, Verification and Validation” (IV&V). Its main purpose is to ensure that the System is being developed in accordance with customer requirements and is well-engineered. IV&V activities are usually performed after the hardware platform has been deployed (post-silicon stage). Compliance issues detected by IV&V on the deployed HW might thus determine severe modifications to the implemented product, with obvious risk to miss the original schedule. Therefore, advancing the IV&V process before the HW is built, could have a positive impact on the production schedule, decreasing the risk of detecting severe non-compliances in the post-silicon stage. Beside the traditional (post-silicon) verification approach, an emerging design approach is to advance IV&V before the HW is deployed by means of virtual-platforms and simulation tools.

This presentation will show the work performed at Elettronica SpA to automate the integration of virtual systems development (VSD) and simulation in its embedded software development process. The approach is based on a combination of metamodels, model transformations and design patterns, the SysML standard and the use of the open source Eclipse framework. The purpose is to derive all the design refinements, including the production code and the code used for simulation and verification from a single set of SysML models. Stereotypes and model transformations are defined to allow the integration of automatically generated interfaces and manually produced code implementing virtual platforms for the simulation of HW/SW heterogeneous systems on the SIMICS platform.

Additional material

  • Presentation slides: [pdf]