A Catalog-based AIG-Rewriting Approach to the Design of Approximate Components

Mario Barbareschi, Salvatore Barone, Nicola Mazzocca, Alberto Moriconi
Rete Ferroviaria Italiana S.p.A., University of Naples "Federico II"

Presentation title

A Catalog-based AIG-Rewriting Approach to the Design of Approximate Components


Mario Barbareschi
Rete Ferroviaria Italiana S.p.A.
Salvatore Barone
University of Naples "Federico II"
Nicola Mazzocca
University of Naples "Federico II"
Alberto Moriconi
University of Naples "Federico II"

Presentation type

Technical presentation


As computational demand and energy efficiency of computer systems are becoming increasingly relevant requirements, traditional design paradigms are bound to become no longer appropriate, as they cannot guarantee significant improvements.

The approximate-computing design paradigm has been introduced as a potential candidate to achieve better performances, by relaxing non-critical functional specifications. Anyway, several challenges need to be addressed in order to exploit its potential.

In this presentation, we propose a systematic and application-independent approximate design approach suitable to combinational logic circuits.

Our approach is based on non-trivial local rewriting of and-inverter graphs (AIG), reducing the number of AIG-nodes and possibly resulting in lower hardware resources requirements. We adopt multi-objective optimization to carefully introduce approximation while aiming at optimal trade-offs between error and hardware-requirements.

We evaluate our approach using different benchmarks, and, in order to measure actual gains, we perform actual synthesis of Pareto-optimal approximate configurations. Experimental results show that the proposed approach allows achieving significant savings, since resulting approximate circuits exhibit lower requirements and restrained error w.r.t. their exact couterparts.

Furthermore, because of architectural differences between FPGA and ASIC technologies, ASIC-tailored approximation techniques are usually unable to provide similar results when targeting FPGAs. We therefore conducted an extensive experimental campaign, aimed to empirically show that the approach is also able to provide good trade-offs between error and FPGA resources, for both generic logic and arithmetic circuits.

Additional material

  • Extended abstract: [pdf]
  • Presentation slides: [pdf]

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